1. Field of the Invention
The present invention relates to a power supply control apparatus, and more particularly to a power supply control apparatus including an output transistor that controls power supply to a load.
2. Description of Related Art
Semiconductors for power supply have been widely employed as power supply control apparatuses that supply power from a power supply to a load. In one field of application, the semiconductors are used to drive actuators or lamps of vehicles. Meanwhile, a counter electromotive voltage is occurred in an output terminal of a power supply control apparatus due to a load having an inductance component such as a solenoid, or an inductance component of a line that connects the load. The power supply control apparatus needs to include an overvoltage protection circuit in order to protect a power supply semiconductor against the counter electromotive voltage. Further, when the power supply is reversely connected (for example, when a battery is reversely connected by error in replacing a battery), it is required to suppress heat generation in the power supply semiconductor to prevent destruction of the power supply control apparatus by conducting the power supply semiconductor.
In the case of using such a power supply control apparatus for vehicles, there is a demand for preventing a wasteful consumption current from occurring when the power supply control apparatus is in a standby state, with a standby current on the order of microamperes.
Japanese Unexamined Patent Application Publication No. 2009-147994 discloses a solution for these demands. FIG. 12 is a circuit diagram corresponding to a power supply control apparatus 1 disclosed in Japanese Unexamined Patent Application Publication No. 2009-147994. As shown in FIG. 12, the power supply control apparatus 1 includes a power supply 10, a load 11, a driver circuit 12, a gate discharge circuit 13, a gate resistor R12, a back gate control circuit 15, a compensation circuit 16, a reverse connection protection circuit 17, a dynamic clamping circuit 19, a switch circuit 20, an output transistor T1, a resistor R10, a resistor R11, a diode D10, a power supply terminal PWR, a ground terminal GND, and an output terminal OUT. The gate resistor R12 may be omitted. The connection of the power supply control apparatus is described in detail in Japanese Unexamined Patent Application Publication No. 2009-147994, and thus the description thereof will be omitted.
Next, operations of the power supply control apparatus 1 will be described. In this case, the operations are classified into two types: an operation performed when the power supply 10 is normally connected; and an operation performed when the power supply 10 is reversely connected. Further, the operation performed when the power supply 10 is normally connected includes the following modes. That is, a conductive mode and a negative voltage surge mode. In the conductive mode, the output transistor T1 is rendered conductive, and power is supplied to the load 11 through the output terminal OUT. In the negative voltage surge mode, a negative voltage surge occurs to the output terminal OUT from the load 11 as a counter electromotive voltage on turn-off, when the output transistor T1 is changed from the conduction state to the non-conduction state. Hereinafter, the operations of the power supply control apparatus 1 are described in each of the three modes.
First, in the conductive mode, when a low-level control signal S2 output from the driver circuit 12 is applied to a gate of a discharge transistor MN1, the discharge transistor MN1 is rendered non-conductive. On the other hand, when a high-level control signal S1 output from the driver circuit 12 is applied to a gate of the output transistor T1, the output transistor T1 is rendered conductive. Thus, in the conductive mode, a voltage of the output terminal OUT is substantially the same to a positive-polarity-side voltage VB of the power supply 10. Further, in the conductive mode, N-type MOS transistors MN5 and MN6 of a second switch unit 15b are rendered conductive, and N-type MOS transistors MN3 and MN4 of a first switch unit 15a are rendered non-conductive. Accordingly, the voltage of the ground terminal GND is applied to a back gate of a compensation transistor MN7. At this time, in the compensation transistor MN7, a terminal coupled to the output terminal OUT serves as the drain, and a terminal coupled to a node C (a node between the reverse connection protection circuit 17 and the resistor R11) serves as the source. Since the voltage of the ground terminal GND is applied to a gate of the compensation transistor MN7, the compensation transistor MN7 is rendered non-conductive. Further, a protection transistor MN8 of the reverse connection protection circuit 17 is rendered non-conductive. Since the gate voltage is lower than the source voltage, a switch transistor MN11 provided in the switch circuit 20 is rendered non-conductive. Hence, the dynamic clamping circuit 19 is deactivated.
Next, the operation under the negative voltage surge mode is described. The negative voltage surge occurs on turn-off, when the output transistor T1 is switched from a conduction state to a non-conduction state. The negative voltage surge is generated due to influences of an inductance of the load 11 and an inductance of a line that connects the load 11. In this case, since the control signal S2 transits from a low level to a high level, the discharge transistor MN1 is rendered conductive. On the other hand, since the control signal S1 transits from the high level to the low level, the output transistor T1 is rendered non-conductive.
When the output transistor T1 is switched from the conduction state to the non-conduction state (turn-off period), due to the influences of an inductance of the load 11 and an inductance of a line that connects the load 11, a counter electromotive voltage of the negative voltage is generated in the output terminal OUT. In the turn-off period, when the voltage of the output terminal OUT is higher than the voltage of the ground terminal GND, the N-type MOS transistors MN3 and MN4 of the first switch unit 15a are rendered non-conductive, and the N-type MOS transistors MN5 and MN6 of the second switch unit 15b are rendered conductive. Thus, a voltage supplied to the back gate of the compensation transistor MN7 by the back gate control circuit 15 is the voltage of the ground terminal GND. When the voltage of the output terminal OUT is below the voltage of the ground terminal GND (negative voltage surge), the N-type MOS transistors MN3 and MN4 of the first switch unit 15a are rendered conductive, and the N-type MOS transistors MN5 and MN6 of the second switch unit 15b are rendered non-conductive. Accordingly, the voltage supplied to the back gate of the compensation transistor MN7 by the back gate control circuit 15 is the voltage of the output terminal OUT. At this time, in the compensation transistor MN7, the output terminal OUT side serves as the source, and the node C side serves as the drain. Since the gate voltage is higher than the source voltage in the compensation transistor MN7, the compensation transistor MN7 is rendered conductive. As a result, the voltage of the node C is equal to that of the output terminal OUT.
When the negative voltage surge is occurred in the output terminal OUT, the gate voltage of the output transistor T1 becomes the negative voltage as well since the discharge transistor MN1 is rendered conductive. At this time, while the protection transistor MN8 of the reverse connection protection circuit 17 is rendered non-conductive, a parasitic diode D8 formed to the protection transistor MN8 is biased in the forward direction. However, the voltage of the node C is substantially the same as the voltage of the output terminal OUT since the compensation transistor MN7 is rendered conductive, and the protection transistor MN8 is deactivated. Since the protection transistor MN8 is deactivated, a path through which the current flows from the ground terminal GND to the output terminal OUT through the parasitic diode D8 of the protection transistor MN8 and the discharge transistor MN1 is interrupted.
On the other hand, since the switch transistor MN11 of the switch circuit 20 has a gate voltage substantially equal to the voltage of the ground terminal GND (0 V, for example), and a source (gate of the output transistor T1) voltage of negative voltage, the switch transistor MN11 is rendered conductive. Thus, the dynamic clamping circuit 19 is activated. When the source-drain voltage of the output transistor T1 becomes equal to or larger than a clamp voltage due to the decrease of the voltage of the output terminal OUT, the diode D11 provided in the dynamic clamping circuit 19 is rendered conductive, and the output transistor T1 is rendered conductive. The clamp voltage here means the sum of the breakdown voltage of the diode D11, the threshold voltage of the switch transistor MN11, and the threshold voltage of the output transistor T1. As stated before, when the negative voltage is generated in the output terminal OUT, a drain-source voltage of the output transistor T1 is clamped to the clamp voltage, thereby protecting the output transistor T1 from overvoltage.
The negative voltage surge is generated until when the energy stored in the inductance is released. When the release of the energy is completed, the voltage of the output terminal OUT is 0 V. Then the output transistor T1 is rendered non-conductive.
Next, the operation under the reverse connection mode will be described. In the reverse connection mode, the positive-polarity-side voltage VB is coupled to the ground terminal GND and a negative-polarity-side voltage VSS is coupled to the power supply terminal PWR. In this case, the diode D10 is rendered conductive, and a voltage of the node B (node on an anode side of the diode D10) is equal to a forward voltage of the diode D10 (0.7 V, for example). Further, a current flows from the ground terminal GND to the power supply terminal PWR through the load 11 and the parasitic diode formed between a back gate and a drain of the output transistor T1. Accordingly, the voltage of the output terminal OUT is equal to a forward voltage of the parasitic diode (0.7 V, for example).
In summary, the voltage of the node B and that of the output terminal OUT become equal to each other (0.7 V, for example). Accordingly, the N-type MOS transistors MN5 and MN6 of the second switch unit 15b are in the non-conduction state, and the N-type MOS transistors MN3 and MN4 of the first switch unit 15a are in the non-conduction state as well.
Further, the voltage of 0.7 V is supplied to a back gate of each of the protection transistor MN8 and the compensation transistor MN7. In this case, in the compensation transistor MN7, the output terminal OUT side serves as the source, and the node C side serves as the drain. Now, the gate voltage is equal to the source voltage in the compensation transistor MN7, and thus the compensation transistor MN7 is rendered non-conductive. On the other hand, although the protection transistor MN8 is rendered non-conductive, the parasitic diode D8 formed in the protection transistor MN8 is biased in the forward direction. Thus, electric charges are supplied from the ground terminal GND to the gate of the output transistor T1 through the parasitic diode D8, and the output transistor T1 is rendered conductive.
From the above description, the power supply control apparatus 1 according to the related art is able to maintain the output transistor T1 to the conduction state, and to prevent heat generation in the reverse connection mode. Furthermore, the power supply control apparatus according to the related art is able to protect the output transistor T1 from overvoltage in the negative voltage surge mode without impairing an overvoltage protection function.